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Integrated Circuit Systems, Inc.
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION
FEATURES
* High speed differential multiplexer. The device can be configured as either a 4:1 or 2:1 multiplexer * Single LVDS output * 4 selectable PCLK, nPCLK inputs with internal termination * PCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Output frequency: >2GHz * Part-to-part skew: 200ps (maximum) * Propagation delay: 800ps (maximum) * Additive phase jitter, RMS: 66fs (typical) * 2.5V operating supply * -40C to 85C ambient operating temperature * Available in both, Standard and RoHS/Lead-Free compliant packages
GENERAL DESCRIPTION
The ICS854057 is a 4:1 or 2:1 LVDS Clock Multiplexer which can operate up to 2GHz and is a HiPerClockSTM member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The PCLK, nPCLK pairs can accept most standard differential input levels. Internal termination is provided on each differential input pair. The ICS854057 operates using a 2.5V supply voltage. The fully differential architecture and low propagation delay make it ideal for use in high speed multiplexing applications. The select pins have internal pulldown resistors. Leaving one input unconnected (pulled to logic low by the internal resistor) will transform the device into a 2:1 multiplexer. The SEL1 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects PCLK0, nPCLK0).
ICS
BLOCK DIAGRAM
VT0 50 PCLK0 nPCLK0 VT1 50 PCLK1 nPCLK1 00 VT2 50 PCLK2 nPCLK2 VT3 50 PCLK3 nPCLK3 SEL1 Pulldown SEL0 Pulldown 50 50 01 10 11 Q nQ 50 50
PIN ASSIGNMENT
VDD PCLK0 VT0 nPCLK0 SEL1 SEL0 PCLK1 VT1 nPCLK1 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD PCLK3 VT3 nPCLK3 Q nQ PCLK2 VT2 nPCLK2 GND
ICS854057
20-Lead TSSOP 4.40mm x 6.50mm x 0.925mm body package G Package Top View
854057AG
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1
REV. A JULY 18, 2005
Integrated Circuit Systems, Inc.
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION
Type Description Positive supply pins. Non-inver ting LVPECL differential clock input. RT = 50 termination to VT0. Termination input. For LVDS input, leave floating. RT = 50 termination to VT0. Inver ting LVPECL differential clock input. RT = 50 termination to VT0 Pulldown Pulldown Clock select input. LVCMOS / LVTTL interface levels. Clock select input. LVCMOS / LVTTL interface levels. Non-inver ting LVPECL differential clock input. RT = 50 termination to VT1. Termination input. For LVDS input, leave floating. RT = 50 termination to VT1. Inver ting LVPECL differential clock input. RT = 50 termination to VT1. Power supply ground. Inver ting LVPECL differential clock input. RT = 50 termination to VT2. Termination input. For LVDS input, leave floating. RT = 50 termination to VT2. Non-inver ting LVPECL differential clock input. RT = 50 termination to VT2. Differential output pairs. LVDS interface levels. Inver ting LVPECL differential clock input. RT = 50 termination to VT3. Termination input. For LVDS input, leave floating. RT = 50 termination to VT3. Non-inver ting LVPECL differential clock input. RT = 50 termination to VT3.
TABLE 1. PIN DESCRIPTIONS
Number 1, 20 2 3 4 5 6 7 8 9 10, 11 12 13 14 15, 16 17 18 19 Name VDD PCLK0 VT0 nPCLK0 SEL1 SEL0 PCLK1 VT1 nPCLK1 GN D nPCLK2 VT2 PCLK2 nQ, Q nPCLK3 VT 3 PCLK3 Power Input Input Input Input Input Input Input Input Power Input Input Input Output Input Input Input
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RT Parameter Input Capacitance Input Pulldown Resistor Input Termination Resistor Test Conditions Minimum Typical 1.5 50 50 Maximum Units pF k
TABLE 3. CONTROL INPUT FUNCTION TABLE
Inputs SEL1 0 0 1 1 SEL0 0 1 0 1 Clock Out PCLKx/nPCLKx PCLK0, nPCLK0 PCLK1, nPCLK1 PCLK2, nPCLK2 PCLK3, nPCLK3
854057AG
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2
REV. A JULY 18, 2005
Integrated Circuit Systems, Inc.
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION
4.6V -0.5V to VDD + 0.5 V 10mA 15mA 73.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V 5%, TA = -40C TO 85C
Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 2.5 Maximum 2.625 60 Units V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 2.5V 5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current SEL0, SEL1 SEL0, SEL1 VDD = VIN = 2.625V VDD = 2.625V, VIN = 0V -150 Test Conditions Minimum 0.7 * VDD -0.3 Typical Maximum VDD + 0.3 0.3 * VDD 150 Units V V A A
TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = 2.5V 5%, TA = -40C TO 85C
Symbol IIH IIL VPP VCMR Parameter Input High Current Input Low Current Peak-to-Peak Voltage Common Mode Input Voltage; NOTE 1, 2 Test Conditions VDD = VIN = 2.625V VDD = 2.625V, VIN = 0V -150 0.15 1.2 1.2 VDD Minimum Typical Maximum 150 Units A A V V
NOTE 1: Common mode input voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is VDD + 0.3V.
854057AG
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3
REV. A JULY 18, 2005
Integrated Circuit Systems, Inc.
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION
Test Conditions Minimum 225 1.125 Typical 325 4 1.25 5 Maximum 425 35 1.375 25 Units mV mV V mV
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 2.5V 5%, TA = -40C TO 85C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change
TABLE 5. AC CHARACTERISTICS, VDD = 2.5V 5%, TA = -40C TO 85C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Input Skew Par t-to-Par t Skew; NOTE 2, 3 Output Rise/Fall Time Output Duty Cycle MUX Isolation 20% to 80% 700MHz f = 500MHz 50 47 49 -55 30 0 622.08MHz, 12kHz - 20MHz 66 40 200 250 53 51 Test Conditions Minimum Typical >2 800 Maximum Units GHz ps fs ps ps ps % % dBm
tjit tsk(i) tsk(pp)
tR / tF odc muxISOLATION
NOTE: All parameters are measured at 1.9GHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the output is measured at the differential cross point. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
854057AG
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4
REV. A JULY 18, 2005
Integrated Circuit Systems, Inc.
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in
0 -10 -20 -30 -40 -50 -60
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 622.08MHz
(12kHz to 20MHz) = 66fs typical
SSB PHASE NOISE dBc/HZ
-70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M 500M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
854057AG
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REV. A JULY 18, 2005
Integrated Circuit Systems, Inc.
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION
PARAMETER MEASUREMENT INFORMATION
VDD VDD nPCLK0: nPCLK3
Qx
2.5V5% POWER SUPPLY + Float GND -
SCOPE
PCLK0: PCLK3
V
PP
Cross Points
V
CMR
LVDS
nQx
GND
2.5V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nPCLKx PCLKx nPCLKy PCLKy nQ Q
tPD2 tPD1 tsk(i)
nQ PART 1 Q nQ PART 2 Q
tsk(pp)
tsk(i) = |tPD1 - tPD2|
INPUT SKEW
nPCLK0: nPCLK3 PCLK0: PCLK3 nQ Q
tPD
PART-TO-PART SKEW
nQ Q
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
PROPAGATION DELAY
854057AG
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. A JULY 18, 2005
Integrated Circuit Systems, Inc.
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION
VDD

out
80% Clock Outputs
80% VOD
DC Input
LVDS
100
VOD/ VOD out
20% tR tF
20%
OUTPUT RISE/FALL TIME
DIFFERENTIAL OUTPUT VOLTAGE SETUP
VDD out
DC Input
LVDS
out
VOS/ VOS
OFFSET VOLTAGE SETUP
854057AG
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7
REV. A JULY 18, 2005
Integrated Circuit Systems, Inc.
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION APPLICATION INFORMATION
2.5V LVDS DRIVER TERMINATION
Figure 1 shows a typical termination for LVDS driver in characteristic impedance of 100 differential (50 single) transmission line environment. For buffer with multiple LDVS driver, it is recommended to terminate the unused output.
2.5V 2.5V LVDS_Driv er + R1 100
-
100 Ohm Differiential Transmission Line
FIGURE 1. TYPICAL LVDS DRIVER TERMINATION
2.5V DIFFERENTIAL INPUT
WITH
BUILT-IN 50 TERMINATION UNUSED INPUT HANDLING
To prevent oscillation and to reduce noise, it is recommended to have pull up and pull down connected to true and complement of the unused input as shown in Figure 2.
2.5V 2.5V R1 680 PCLK VT nPCLK
R2 680
Receiver with Built-In 50 Ohm
FIGURE 2. UNUSED INPUT HANDLING
854057AG
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8
REV. A JULY 18, 2005
Integrated Circuit Systems, Inc.
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION
50 terminations driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL INPUT WITH BUILT-IN 50 TERMINATIONS INTERFACE
The PCLK /nPCLK with built-in 50 terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS PCLK/nPLCK input with built-in
3.3V or 2.5V
2.5V
2.5V
2.5V
Zo = 50 Ohm IN Zo = 50 Ohm LVDS VT nIN
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN 2.5V LVPECL R1 18
Receiver With Built-In 50 Ohm
Receiver With Built-In 50 Ohm
FIGURE 3A. HIPERCLOCKS PCLK/nPCLK INPUT WITH BUILT-IN 50 DRIVEN BY AN LVDS DRIVER
FIGURE 3B. HIPERCLOCKS PCLK/nPCLK INPUT WITH BUILT-IN 50 DRIVEN BY AN LVPECL DRIVER
2.5V
2.5V
2.5V
2.5V
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN CML - Open Collector
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN CML - Built-in 50 Ohm Pull-up
Receiver With Built-In 50 Ohm
Receiver With Built-In 50 Ohm
FIGURE 3C. HIPERCLOCKS PCLK/nPCLK INPUT WITH BUILT-IN 50 DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 3D. HIPERCLOCKS PCLK/nPCLK INPUT WITH BUILT-IN 50 DRIVEN BY A CML DRIVER WITH BUILT-IN 50 PULLUP
2.5V R1 25 Zo = 50 Ohm IN Zo = 50 Ohm R2 25 VT nIN
2.5V
SSTL
Receiver With Built-In 50
FIGURE 3E. HIPERCLOCKS PCLK/nPCLK INPUT WITH BUILT-IN 50 DRIVEN BY AN SSTL DRIVER
854057AG
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9
REV. A JULY 18, 2005
Integrated Circuit Systems, Inc.
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION
AND
RECOMMENDATIONS FOR UNUSED INPUT INPUTS:
OUTPUT PINS OUTPUTS:
LVDS OUTPUT All unused LVDS outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
PCLK/nPCLK INPUT: For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from PCLK to ground.
SCHEMATIC EXAMPLE
Figure 4shows a schematic example of the ICS854057. In this example, the PCLK0/nPCLK0 and PCLK1/nPCLK1 inputs are
used. The decoupling capacitors should be physically located near the power pin.
VDD VDD LVDS VDD U1 Zo = 50 R1 1K 1 2 3 4 5 6 7 8 9 10 VDD PCLK0 VT0 nPCLK0 SEL1 SEL0 PCLK1 VT1 nPCLK1 GND VDD PCLK3 VT3 nPCLK3 Q nQ PCLK2 VT2 nPCLK2 GND 20 19 18 17 16 15 14 13 12 11 R2 680 R1 1K LVPECL Zo = 50 C1 0.1u C2 0.1u R6 18 (U1,1) VDD (U1,20) R4 680 ICS854057 VDD R1 680 R3 680 VDD
Zo = 50
Zo = 50 R5 100
+
VDD
Zo = 50 LVDS
Zo = 50
VDD=2.5V
FIGURE 4. EXAMPLE ICS854057 LVDS SCHEMATIC
854057AG
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REV. A JULY 18, 2005
Integrated Circuit Systems, Inc.
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION RELIABILITY INFORMATION
TABLE 7.
JAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0 200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
114.5C/W 73.2C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS854057 is: 346
854057AG
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REV. A JULY 18, 2005
Integrated Circuit Systems, Inc.
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION
20 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 Millimeters Minimum 20 1.20 0.15 1.05 0.30 0.20 6.60 Maximum
Reference Document: JEDEC Publication 95, MO-153
854057AG
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REV. A JULY 18, 2005
Integrated Circuit Systems, Inc.
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION
Marking Package 20 lead TSSOP 20 lead TSSOP 20 lead "Lead-Free" TSSOP 20 lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS854057AG ICS854057AGT ICS854057AGLF ICS854057AGLFT ICS854057AG ICS854057AG ICS854057AGL ICS854057AGL
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 854057AG
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REV. A JULY 18, 2005

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